By Topic

Bridging the information gap between buffer and flash translation layer for flash memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Xue-Liang Liao ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China ; Shi-Min Hu

Flash memory has been widely used as storage media in consumer devices, whereas its erase-before-update characteristic degrades its performance. Buffer and FTL (Flash Translation Layer) are two important techniques to improve the performance of flash memory. However, in the traditional architecture, the buffer and FTL work independently, resulting in an information gap which affects the efficiency of garbage collection in flash memory. This paper proposes a new architecture to bridge the information gap between the buffer and the FTL. In the new architecture, the buffer manager provides several replacement candidates instead of one to the FTL, and the FTL makes and performs a decision according to these candidates and the physical information of flash memory. Experiments show that the new architecture can reduce the garbage collection overhead by up to 40%.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:57 ,  Issue: 4 )