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This paper presents the implementation and experimental evaluation of an advanced MIMO detector for wireless LAN systems. The proposed detector architecture is based on the well-known lattice-reduction aided MMSE method. Several optimizations at both algorithmic and architectural level are presented which result in an efficient VLSI design able to meet the timing requirements of a practical OFDM-based wireless LAN receiver while keeping complexity at moderate levels. Moreover, the detector offers built-in compensation for transmitter impairments such as nonlinear power amplifier characteristics, hence providing a full and cost-effective solution for practical systems. The described solution is implemented on an FPGA-based IEEE802.11n prototype and evaluation results comparing performance of both conventional MMSE and reduced-lattice detection under several propagation scenarios are presented. Experimental results show significantly lower error rates at the receiver for the advanced detector, or equivalently a lower number of required receiver antenna elements for a given performance target, hence resulting in lower cost, physical size and energy consumption1.