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Parallel pipelined array architectures for real-time histogram computation in consumer devices

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4 Author(s)
Cadenas, J.O. ; Sch. of Syst. Eng., Univ. of Reading, Reading, UK ; Sherratt, R.S. ; Huerta, P. ; Wen-Chung Kao

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle 1.

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Consumer Electronics, IEEE Transactions on  (Volume:57 ,  Issue: 4 )