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Onboard error detection and correction (EDAC) devices aim to secure data transmitted between the central processing unit (CPU) of a satellite onboard computer (OBC) and its local memory. A follow-up is presented here of some low-complexity EDAC techniques for application in random access memories (RAMs) onboard the Algerian microsatellite Alsat-1. The application of a double-bit EDAC method is described and implemented in field programmable gate array (FPGA) technology. The performance of the implemented EDAC method is measured and compared with three different EDAC strategies, using the same FPGA technology. A statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard Alsat-1 is given. A new architecture of an onboard EDAC device for future Earth observation small satellite missions in low Earth orbits (LEO) is described.