By Topic

Reducing hardware complexity of motion estimation algorithms using truncated pixels

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
He, Z. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong ; Liou, M.L.

Traditional block-matching motion estimation algorithms search motion vectors using full precision pixels, normally 8-bits-per-pixel. In this paper, we introduce an approach for block-matching motion estimation using truncated pixels. The full-search algorithm is employed for discussion. We investigate the system performance with different number of truncated bits. Simulation results show that the matching error decreases exponentially when the number of truncated bits is reduced, and the number of truncated bits of 4 can be chosen as a reasonable solution for motion vector searching. We also discovered that the average PSNR of the decoded video sequences degrades only 0.03%-2.1%, while the equivalent gate count drops 46% for many of the existing VLSI architectures!

Published in:

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on  (Volume:4 )

Date of Conference:

9-12 Jun 1997