Simple hardware verification platform using SystemVerilog

A simplified hardware verification platform based on layered approach is implemented using SystemVerilog. SystemVerilog unifies several proven hardware design and verification languages in the form of extensions to Verilog HDL. The importance of a verification platform based on OOP technique is increasing for high-level functional verification. The proposed platform consists of components such as generator, driver, monitor and checker which are connected by channels. The structure and test procedure based on Teal/Truss are changed to be as simple as possible for those who are not familiar with OOP to understand and use the platform easily.