By Topic

Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Dimitris Bekiaris ; Microprocessors & Digital Syst. Lab., Nat. Tech. Univ. of Athens, Athens, Greece ; George Economakos ; Efstathios Sotiriou-Xanthopoulos ; Dimitrios Soudris

Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfigurable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the data path of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi Vth components, for the design of low-power morphable multipliers. Experimentation with these multipliers in a high-level synthesis flow show that they can offer performance, area and power improvements compared to alternative architectures, making them valuable building blocks for hardware synthesis.

Published in:

2011 International Conference on Reconfigurable Computing and FPGAs

Date of Conference:

Nov. 30 2011-Dec. 2 2011