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n-p-n Array Yield Improvement in a 0.18-μm Deep Trench SiGe BiCMOS Process

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5 Author(s)
Dong Gan ; TowerJazz Semicond., Newport Beach, CA, USA ; Chun Hu ; Parker, G.E. ; Pao, H.H.
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The deep trench (DT) process module shows a strong impact on SiGe BiCMOS n-p-n array yield. DT liner oxidation introduces large tensile stress at the top of DT corners and in the vicinity of intrinsic SiGe base/collector regions. The increased tensile stress can result in dislocations in silicon. By replacing the 100-nm wet oxidation DT liner with a TEOS deposition liner, n-p-n array collector-emitter leakage yield can be improved from 64% to 94% in the investigated 0.18-μm DT SiGe BiCMOS process, comparable to the yield of a non-DT low-cost SiGe BiCMOS process.

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Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 3 )