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Variability in back-gated thin-body capacitorless DRAM cell performance is investigated via TCAD simulation. Sources of variability considered include variations in front gate oxide thickness, body thickness, buried oxide thickness, and gate-sidewall spacer width, as well as random dopant fluctuations. Bipolar junction transistor-based cell operation is most sensitive to variations in body thickness and buried oxide thickness. Retention time for an optimized 22 nm-node cell design is predicted to be reduced by approximately 63% due to process-induced variations.