A novel single slope ADC design for wide dynamic range CMOS image sensors

This paper presents a novel single slope ADC design for dual-exposure wide dynamic range CMOS image sensor (CIS). The proposed design achieves column-wise high/low illuminated pixel detection, and only the `adequate' signal (lone-or short-exposure) is digitized. Since high/low-illuminated pixel detection is accomplished by the proposed SS ADC, each pixel is read out once during a wide DR frame and the power dissipation is hence reduced. The dynamic range expansion ratio is programmable and depends on the time ratio of long-exposure to short-exposure period. A 160×140 wide DR CIS chip with proposed SS ADC was realized in 0.18um CIS technology. It achieves a sensitivity of 5.33V/lx·s and a noise floor of 15e- at 60frames/s. The measured dynamic range is 95dB with a 40dB boost by setting the exposure time ratio as 100. The resulting DNL is +0.7/-0.6 LSB and the column-FPN is below 0.1%.