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A digital PLL with a multi-delay coarse-fine TDC

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3 Author(s)
Ying Wu ; Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden ; Ping Lu ; Andreani, P.

A 5GHz digital frequency synthesizer achieving a low noise for wireless RF application is presented. This architecture uses a multi-delay coarse-fine Time-to-Digital Converter (TDC) to achieve both the large detection range and fine resolution. A Digitally Controlled Oscillator (DCO) based on capacitive degeneration in LC-Tank is also implemented. The DCO achieves frequency quantization step of 300 Hz without any dithering. Simulated phase noise at 5 GHz carrier frequency is -125 and -151 dBc/Hz at 1 MHz and 20 MHz offset, respectively. The Digital phase-locked loop (DPLL) is realized in 90nm CMOS process and consumes 14mA from a 1.2V supply.

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Date of Conference:

14-15 Nov. 2011