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Implementation and Test of Appearance-Based Vision Algorithms Using High-Level Synthesis in FPGA

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5 Author(s)
Ortiz-Lopez, E. ; Electron. Dept., DICIS Univ. de Guanajuato, Salamanca, Mexico ; Ibarra-Manzano, M.-A. ; Andrade-Lucio, J.A. ; Cervantes, J.G.A.
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This article presents an architecture to detect objects from images based on color and texture features. This architecture is simplified and efficient as a result of the optimization of Adequacy of Sum and Difference of Histograms(ASDH) for embedded systems. Our architecture was prototyped using LabVIEW FPGA which is a practical tool to develop high-level synthesis. We take advantage of LabVIEW FPGA to do rapid prototyping and implement the architecture and to make a general comparison among this architecture implemented with Hardware Description Language (HDL) and LabVIEW FPGA, this lets us analyze if the use of high level synthesis improve the systems performance. The use of high level synthesis give us an interesting option to improve in digital design made it the time of prototyping more shortly, efficiently and flexible for example in applications for vision systems.

Published in:

Electronics, Robotics and Automotive Mechanics Conference (CERMA), 2011 IEEE

Date of Conference:

15-18 Nov. 2011