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We found the dynamic-energy increase in SRAM caused by VDD reduction under 0.7V. This is caused by the random variability and the total (dynamic + leakage) energy increase is estimated to be 95% at 0.5V. A Bitline Amplitude Limiter capable of compensating this energy degradation is proposed. This limiter reduces dynamic energy by suppressing excess bitline amplitude. And it reduces leakage automatically even during the operation. The speed penalty for introducing this circuit is estimated to be 7%. And the area penalty is less than 2%. The total energy reduction of 26% has been confirmed with simulations at 0.5V. The circuit has been implemented with 40nm CMOS technology and the energy reduction of 19% is confirmed by measurements.
Date of Conference: 14-16 Nov. 2011