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A low power SRAM operating at the logic supply voltage of 0.5V-1.0V without chip by chip trimming has been developed. A Dynamic Cell Stability Monitor controls wordline level adaptively by sensing the data flip in reference memory cells. The cell failure rate in every process corner is improved. A Modulated Wordline Level Scheme for Replica Cell optimizes sense timing and the operating frequency is improved by 18% at 1.0V. A Multiple Memory Cell Access Mode pushes the minimum operating cell supply voltage down to 0.5V. A 40nm 2Mb SRAM test chip with 0.24um2 cell has demonstrated 0.5V operation.