By Topic

A leakage-current-recycling phase-locked loop in 65nm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
I-Ting Lee ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Yun-Ta Tsai ; Shen-Iuan Liu

A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider and a dual-mode phase-frequency detector. This PLL is fabricated in a 65nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640MHz are 52.2ps and 9.6ps, respectively. Its power consumption is 1mW for a 1.2V supply voltage.

Published in:

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Date of Conference:

14-16 Nov. 2011