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Quad Full-HD transform engine for dual-standard low-power video coding

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3 Author(s)
Rahul Rithe ; Massachusetts Institute of Technology 77 Massachusetts Ave., Cambridge, MA 02139, USA ; Chih-Chi Cheng ; Anantha Chandrakasan

Transform engine is a critical part of the video codec and increased coding efficiency often comes at the cost of increased complexity in the transform module. H.264/AVC and VC-1 are two recent video coding standards that employ variable size and hierarchical transforms to achieve coding efficiency. In this work we propose a shared-reconfigurable transform engine using the structural similarity and symmetry of the transforms for H.264/AVC and VC-1. An approach to eliminate the need for an explicit transpose memory in 2D transforms is proposed. Data dependency is exploited to reduce power consumption. Ten different versions of the transform engine, such as with and without hardware sharing, with and without transpose memory, are implemented in the design. The design is fabricated using commercial 45nm CMOS technology and all implemented versions are verified. The shared-reconfigurable transform engine without transpose memory supports Quad Full-HD (3840 × 2160) video encoding at 30fps, while operating at 0.52V, with measured power of 214μW. Hardware sharing saves 30% area compared to individual H.264 and VC-1 implementations combined. Eliminating an explicit transpose memory using a 2D (8×8) output buffer reduces area by 23% and power by 26%. Several of ideas proposed here can potentially be extended to future video coding standards such as HEVC.

Published in:

Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian

Date of Conference:

14-16 Nov. 2011