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A low-voltage operation, small-die-area, fully integrated Phase-Locked Loop (PLL) as a clock generator is described in an advanced 32nm CMOS technology. The PLL employs a fully digital, 6-bit automatic frequency calibrator (AFC), and varactors for frequency fine-tuning. To improve the performance and lower down the cost in mobile SoC applications, the PLL is capable of operating at a supply voltage of 0.8V over production test with only regular threshold voltage (RVT) transistors. The power consumption is measured at 0.7mW when a VCO oscillates at 700MHz frequency under a supply voltage of 0.8V. The total die size is 200μm by 200μm, including global power/ground routing, input ESD cells and on-chip power decoupling capacitors. Production tests show that the PLL consumes less than 0.7mW with a 0.8V supply and rms period jitter is less than 3.3ps at an output frequency of 700MHz.