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AES-512: 512-bit Advanced Encryption Standard algorithm design and evaluation

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3 Author(s)
Moh'd, A. ; Eng. Math. & Internetworking, Dalhousie Univ., Halifax, NS, Canada ; Jararweh, Y. ; Tawalbeh, L.

This paper presents an FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm. The efficient hardware that implements the algorithm is also proposed. The new algorithm (AES-512) uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase. AES-512 will be suitable for applications with high security and throughput requirements and with less chip area constrains such as multimedia and satellite communication systems. An FPGA architectural for AES-512 was developed using VHDL, and synthesized using Virtix-6 and Virtex-7 chips. AES-512 show tremendous throughput increase of 230% when compared with the implementation of the original AES-128.

Published in:

Information Assurance and Security (IAS), 2011 7th International Conference on

Date of Conference:

5-8 Dec. 2011