By Topic

Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Jannaty, P. ; Dept. of Phys., Brown Univ., Providence, RI, USA ; Sabou, F.C. ; Le, S.T. ; Donato, M.
more authors

As CMOS technology continues the path of miniaturization, noise-induced fluctuations raise heightened reliability concerns. In previous work, an analytical framework based on Markov queueing theory and Poisson shot noise was presented to model the probabilistic behavior of a CMOS flip-flop operated in the subthreshold regime. In this paper, this model is extended to also account for the above-threshold shot noise, where the noise distribution is no longer Poissonian. The formulas for the time-dependent charging and discharging of node capacitors of a four-transistor flip-flop are derived for different regimes of operation characterized by distinct Fano factors. The statistics of electron arrival and departure at node capacitors is incorporated in an algebraic representation based on Markov queueing theory to map the effects of charge fluctuations on the logic stability of a flip-flop. This framework is used in Part II of this work to investigate failure in time for end-of-roadmap CMOS at the 10-nm gate-length scale.

Published in:

Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 3 )