By Topic

Threshold Voltage Fluctuations in Localized Charge-Trapping Nonvolatile Memory Devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Meir Janai ; Spansion Israel Ltd., Netanya, Israel ; Meng Chuan Lee

Threshold voltage fluctuations are studied in localized charge-trapping nonvolatile memory devices. Intensive program/erase cycling followed by high-temperature bake shifts the mean Vt of programmed bits and increases the variance of the Vt distribution. After long enough bake, the Vt decay saturates, and the mean Vt and the variance stabilize. Upon continuing bakes, Vt's of individual bits are found to fluctuate up and down while the envelope remains fixed. The formation of a stable envelope of randomly fluctuating bits is modeled in terms of charge displacements of trapped electrons confined to the cells' nitride storage layer. Implications to product reliability under high-temperature stress are discussed.

Published in:

IEEE Transactions on Electron Devices  (Volume:59 ,  Issue: 3 )