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Flying-Adder direct period synthesis is an emerging frequency synthesis technique. It is a mixed-signal technology that directly constructs the output clock period based on a multi-inputs reference. Owing to its open loop style and the usage of Time-Average-Frequency, this technique bears two important features: fine frequency resolution and instantaneous response. Although it has been used in commercial products for over a decade, the important issue associated with design/layout mismatch among its multi-inputs has not been studied in depth. In this paper, through a 55 nm Flying-Adder implementation, the cause of the mismatch is investigated. A mismatch model is created. Based on the model, the mismatch's impact is studied both in time and frequency domain. The experimental data from the chip is used to verify the observations from the analysis. Some useful insights are summarized in the end which will be useful in guiding future designs for commercial products. This study could also be helpful in developing a general theory for this problem.