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Will physical scalability sabotage performance gains?

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1 Author(s)
Matzke, D. ; Texas Instrum. Inc., USA

The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will soon be impossible to maintain one global clock over the entire chip, and sending signals across a billion-transistor processor may require as many as 20 cycles

Published in:

Computer  (Volume:30 ,  Issue: 9 )