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High-level design and synthesis of a resource scheduler

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3 Author(s)
João Paulo Pizani Flor ; Software/Hardware Integration Lab, Federal University of Santa Catarina, Florianopolis, Brazil ; Tiago Rogério Mück ; Antônio Augusto Fröhlich

Given the increasing complexity of current embedded systems, hardware design is being pushed to a higher level of abstraction, with High-Level Synthesis tools enabling hardware synthesis from untimed C++. Still, HLS technology does not provide a clear methodology to derive both hardware and software implementations from a single high-level code. This paper describes the design, implementation and evaluation of a resource scheduler that has a single C++ description and is automatically implementable in both software and hardware.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011