By Topic

All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Bushnaq, S. ; Electr. Eng., Univ. of Tokyo, Tokyo, Japan ; Ikeda, M. ; Asada, K.

In this paper, we present an all-digital Power Amplifier (PA) that is fully integrated on chip using 0.18 μm CMOS process. This PA consists of 8 output-connected all-digital inverters controlled by an 8-phase clock generated using a multistage Phase Interpolator (PI). Experimentally, our architecture showed power consumption less than 0.03 mW/MHz, and tuning range from 400 to 900 MHz. This architecture will be used with our wireless transceiver that applies a modified BPSK as modulation.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011