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A multi-bit error tolerant register file for a high reliable embedded processor

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4 Author(s)
Esmaeeli, S. ; Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran ; Hosseini, M. ; Vosoughi Vahdat, B. ; Rashidian, B.

The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1-5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the register width. Two additional bits for each data register have been used to store the information for a narrow-width value. Each 64-bit data in register file has its unique 64-bit extended Hamming code that is stored in another register file in a bit-interleaved manner. Two copies of narrow-width values can be stored in one register and each copy has its unique extended Hamming code in other register file. Proposed method has been tested using fault injection simulation with SPEC2000 benchmarks. Error probability of a word that stores generated values for register file in SPEC2000 benchmarks and is protected with proposed method is less than the error probability of the same word that is protected with TMR or various extended Hamming codes. The implementation on a Xilinx Virtex-4 FPGA shows that the area overhead of a register file with 64-bit wide and more than 64-word entry that is protected with proposed method is less than the area overhead of the same register file that is protected with TMR. Error detection and correction is performed in parallel with execute stage to prevent performance degradation. More than 99% of errors in adjacent 32 bits in data or extended Hamming code registers can be corrected with the proposed method. Presented method employs pure combinational l- gics and can be used for 16-bit and 32-bit register files too.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011