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A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme

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5 Author(s)
Xu Wang ; Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China ; Jianfei Jiang ; Zhigang Mao ; Bingjing Ge
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For a conventional SRAM, bit-lines dissipate the largest part of power consumption, since they are long lines with parasitical capacitance. Furthermore, the bit-lines consume more power in write cycle than in read cycle. A new charge-recycling method is proposed to reduce bit-line power consumption. The proposed SRAM pre-charge the bit-lines to VDD or GND respectively, they share the charge of adjacent bit-lines in write cycle. This is different from the former charge-recycling technique, because it does not need the additional voltage supply except VDD. SRAM cells also dissipate a lot of leakage power consumption in inactive cycle. The proposed SRAM uses non uniform cell method to reduce gate leakage. In this paper, a 64kb (4k*16bits) 1-port SRAM is implemented with 100nm CMOS technology, the simulation results show that it reduces 32.9% leakage for SRAM cell in inactive mode, and 22% total power consumption to the conventional SRAM.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011