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A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC achieves 56.04dB signal-to-noise ratio (SNDR), 9.02 effective numbers of bits (ENOB) and INL/DNL of less than 1 LSB, while consuming only 3.9 mW from a 1-V power supply. The Figure-of-Merit (FOM) value is less than 0.19 pJ/Conversion.