By Topic

Hardware-accelerated address-event processing for high-speed visual object recognition

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Michael Hofst√§tter ; AIT Austrian Institute of Technology GmbH, Vienna, Austria ; Martin Litzenberger ; Daniel Matolin ; Christoph Posch

This paper presents a hardware implementation for high-speed, event-based data processing. A full-custom Address-Event (AER) processing system (GAEP) features a 10ns-resolution 33M/5.125M events·s-1 peak/sustained event rate sensor data interface for precision time-stamping of asynchronous sensor data and implements hardware-accelerated event pre-processing including rate dependent IRQ generation and address masking for ROI/RONI. The pre-processing functions are implemented in dedicated hardware and operate without loading the actual processor device, a SPARC-compatible general-purpose micro-processor. The complete SoC is implemented in 0.18μm standard CMOS technology. We present a camera system comprising the AER processor and a bio-inspired dynamic vision sensor in an exemplary high-speed vision application related to shape detection / object recognition. Relevant details of the system architecture and performance results characterizing the vision system in a real-world machine vision application are presented.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011