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A low-power 2 GHz discrete time weighting system dedicated to Sampled Analog Signal Processing

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6 Author(s)
Y. Abiven ; IMS Laboratory, University of Bordeaux, Talence, France ; F. Rivet ; Y. Deval ; D. Dallet
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Multi-standard applications encounter several developments in the wireless systems. A single receiver is required for any standard of communication. Software Radio (SR) is an illustration of this concept. This paper presents a design methodology to ease the design of a flexible RF receiver based on an analog discrete time Fast Fourier Transform (FFT). A proposed architecture named SASP (Sampled Analog Signal Processor) targets the previously exposed concept for wireless constraints. The FFT algorithm brings an analog weighting unit which is the most power hungry part in such an analog discrete time processor.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011