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Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system

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3 Author(s)
Devlin, B. ; Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan ; Ikeda, M. ; Asada, K.

In this paper we present an autonomous watchdog circuit for error robustness which can detect logic errors caused by power supply noises and soft errors, with the smallest overheads compared to current research. The proposed watchdog circuit is realized with the dual-pipeline self synchronous system, without the need to duplicate logic. The watchdog circuit prevents error propagation through the logic chain, and errors are successfully detected. Error tolerance to power supply bounce is measured at 67% at 1.2V. Circuit size and energy-per-operation is increased 6.9% and 16% respectivley for the case of a 65nm self synchronous FPGA.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011