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This paper deals with a digital clock and data recovery (CDR) circuit for low-to-moderate data rate applications. The design is based on the analogy between an analog charge-pump based phase-locked loop (CPPLL) and an all-digital phase-locked loop (ADPLL). The whole CDR design has been implemented and tested using an Altera® Stratix Development Board. Measurements show a recovered clock peak-to-peak jitter of 10 ns (1% UI) for an input data rate of 1 Mbps.