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An all-digital clock and data recovery circuit for low-to-moderate data rate applications

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4 Author(s)
Tall, N. ; IM2NP, Aix-Marseille Univ., Marseille, France ; Dehaese, N. ; Bourdel, S. ; Bonat, B.

This paper deals with a digital clock and data recovery (CDR) circuit for low-to-moderate data rate applications. The design is based on the analogy between an analog charge-pump based phase-locked loop (CPPLL) and an all-digital phase-locked loop (ADPLL). The whole CDR design has been implemented and tested using an Altera® Stratix Development Board. Measurements show a recovered clock peak-to-peak jitter of 10 ns (1% UI) for an input data rate of 1 Mbps.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011

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