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Estimating the design value(s) of the shunt-peaking inductor(s) in CMOS trans-impedance amplifier system by placement of poles and zeros

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2 Author(s)
Raut, R. ; Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada ; Talukder, M.A.H.

This article provides a guideline towards estimating the design value(s) of the shunt-peaking inductor(s) used in a wide-band CMOS amplifier system. Mathematical analysis and numerical technique followed by circuit simulation, have been used to demonstrate the feasibility of the approach. The procedure applied to a common-gate amplifier in 0.5 micron CMOS technology produces a simulation result with 51.8 dBΩ gain, 4.32 GHz bandwidth, a peaking <; 1dB, with 2.8 mW of DC power. Similarly, the design of an interstage PI configuration of inductors, demonstrates a -3dB bandwidth of 37 GHz, peaking <;0.3 dB with a total inductance of 2.24 nH.

Published in:

Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on

Date of Conference:

11-14 Dec. 2011