By Topic

SP-HV: A Scalable Surface-Potential-Based Compact Model for LDMOS Transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Wei Yao ; School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ, USA ; Gennady Gildenblat ; Colin C. McAndrew ; Alexandra Cassagnes

This paper introduces a scalable compact model of lateral double-diffused MOS (LDMOS) transistors. The new model, i.e., the Surface-Potential-based High-Voltage MOS (SP-HV), is constructed from a surface-potential-based bulk MOS field-effect transistor model, i.e., PSP, and a nonlinear resistor model, i.e., R3. Extensions are made to both PSP and R3 for improved modeling of LDMOS devices, and one internal node is introduced to connect the two component models. The new model is validated by comparison to technology computer-aided design (TCAD) simulations and experimental data. Quasi-saturation, self-heating, impact ionization current in the drift region, and complex behavior of transcapacitances are accurately modeled by SP-HV.

Published in:

IEEE Transactions on Electron Devices  (Volume:59 ,  Issue: 3 )