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The core of every microprocessor, digital signal processor (DSP), and data-processing application-specific integrated circuit (ASIC) is its data path. At the heart of data-paths and addressing units are arithmetic units, such as comparators, adders, and multipliers and at the heart of arithmetic circuits are adders. The main constraints of all adders are their speed, performance, power consumption and die area. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. This paper involves the design of high speed, parallel-prefix adders such as Brent-Kung, Sklansky, Kogge-Stone and Ling adders, by Kogge-Stone implementation, using CMOS logic and transmission gate logic. The design and simulations are done using deep sub micron technology file. The power, area and delay for the two implementations are compared and it is found that the power, area and delay in the transmission gate logic is much lower than those in CMOS logic. This is done for 8, 16 and 32 bit adders. All the circuits are implemented using Tanner EDA and simulated in 130nm using TSMC MOSIS Level-49 model in TSPICE simulator.