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Design and Implementation of the Low Power 0.64mW, 380 KHz Continuous Time Sigma Delta ADC

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3 Author(s)
Aniruddha Kanhe ; Dept. of Electron. & Telecommun., NIT, Raipur, India ; Bibhudendra Acharya ; R. B. Deshmukh

In this paper a low power Sigma Delta Modulator is presented. The reported ADCs which are used in high bandwidth applications ranging from KHz to MHz consume about 10 to 70mW. The modulator designed in this work consumes 0.64mW from a 1.8V supply and operates at 380 KHz with an over-sampling ratio of 64 and a single bit quantizer in 180nm technology for portable and digital radio application. Discrete-time and continuous-time sigma-delta modulators are compared to highlight the power advantages and design challenges in the continuous-time approach. For testing purpose the coherent sampling is done to get the FFT plot of the output signal.

Published in:

2011 Fourth International Conference on Emerging Trends in Engineering & Technology

Date of Conference:

18-20 Nov. 2011