Referenced Items are not available for this document.
In this paper, a fully digital delay line based temperature sensor is presented for on-chip thermal monitoring. Unlike previous delay line temperature sensors, the proposed design employs a 2N to N tab decoding along with counter and in this way dynamic power is saved by a factor of 2N. Post-layout simulation for a 65nm CMOS design shows that the proposed sensor consumes 0.02 nJ energy per conversion and it has a resolution of 1.0 °C with errors less than ±3.0 °C over a temperature range from 0 to 100 °C.
Published in:
Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of
Date of Conference: 17-18 Nov. 2011
- Page(s):
- 1 - 2
- ISSN :
- Pending
- E-ISBN :
- 978-1-4577-1996-7
- Print ISBN:
- 978-1-4577-1998-1
- INSPEC Accession Number:
- 12461419
- Conference Location :
- Tianjin
- Digital Object Identifier :
- 10.1109/EDSSC.2011.6117665
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
