By Topic

A 65nm CMOS low power delay line based temperature sensor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shuang Xie ; Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada ; Wai Tung Ng

In this paper, a fully digital delay line based temperature sensor is presented for on-chip thermal monitoring. Unlike previous delay line temperature sensors, the proposed design employs a 2N to N tab decoding along with counter and in this way dynamic power is saved by a factor of 2N. Post-layout simulation for a 65nm CMOS design shows that the proposed sensor consumes 0.02 nJ energy per conversion and it has a resolution of 1.0 °C with errors less than ±3.0 °C over a temperature range from 0 to 100 °C.

Published in:

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Date of Conference:

17-18 Nov. 2011