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Instruction Scheduling on Variable Latency Functional Units of VLIW Processors

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1 Author(s)
Mujadiya, N.V. ; Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol.-Hyderabad, Hyderabad, India

In Very Long Instruction Word (VLIW) processors, based on the available instruction-level parallelism in programs, compilers schedule operations onto different functional units. By assuming all the functional units of same kind and having the same latency, the conventional list-scheduling algorithm selects the first available (free) functional unit to schedule an operation. But, in advanced process technologies due to process variation, functional units of same kind may have different latencies. In such situation, conventional scheduling algorithms may not yield good performance. In this work, we address an interesting problem of how to schedule operations on variable latency functional units of a VLIW processor. We propose an algorithm to schedule operations on non-uniform latency functional units and compare our algorithm with the conventional list-scheduling algorithm.

Published in:

Electronic System Design (ISED), 2011 International Symposium on

Date of Conference:

19-21 Dec. 2011

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