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An Increment/Decrement circuit is a common building block in many digital systems like address generation unit which are used in micro controllers and microprocessors. Similarly 2's complement and priority encoder circuits are used in many applications. This paper presents an improvement to the decision block of the existing INC/DEC architectures. This improvement results in up to 48% reduced delay and 50% reduced power delay product. This paper also proposes a reconfigurable INC/DEC/2's complement/Priority encoder circuit which uses the new proposed decision blocks.
Date of Conference: 19-21 Dec. 2011