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Testing and Design-for-Testability Techniques for 3D Integrated Circuits

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2 Author(s)
Brandon Noia ; Dept. Electr. & Comput. Eng., Duke Univ., Durham, NC, USA ; Krishnendu Chakrabarty

Technology scaling for higher performance and lower power consumption is being hampered today by the bottleneck of interconnect lengths. 3D integrated circuits (3DICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming the interconnect bottleneck. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3Dintegration commercially viable. This paper presents a survey of test challenges for 3D ICs and describes recent innovations on various aspects of 3D testing and DfT. Topics covered include pre-bond testing (BIST and TSV probing), optimizations for post bond testing, and cost modeling for 3D integration and associated test flows.

Published in:

2011 Asian Test Symposium

Date of Conference:

20-23 Nov. 2011