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2.5D Stacked ICs (2.5D-SICs) consist of multiple active dies (or 3D towers of active dies), which are placed side-by-side on top of and interconnected through a passive silicon interposer base which contains Through-Silicon Vias (TSVs). A previously presented post-bond test and Design-for-Test(DfT) strategy for such 2.5D-SICs implements a serial Test Access Mechanism (TAM) for interposer and micro-bump testing. In addition, it tries to identify an as-wide-as-possible set of functional interposer interconnects that can be reused as parallel TAMs to the various dies. In this paper, we extend that approach with the concept of Multi-Visit TAMs, i.e., parallel TAMs which are allowed to visit the same die more than once. For minimal additional hardware costs, the Multi-Visit TAMs succeed significantly more often in identifying a valid parallel TAM and achieve significantly lower test lengths.