Scheduled System Maintenance:
On Wednesday, July 29th, IEEE Xplore will undergo scheduled maintenance from 7:00-9:00 AM ET (11:00-13:00 UTC). During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Nemati, N. ; Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran ; Navabi, Z.

Test and testability are essential concerns for design in any abstraction level, and are even more challenging for high level designs. Because of complexity of today's designs, design at ESL (electronic system level) using transaction level modeling (TLM) has become a focal point of today's system level designers. However, there are no standard test methods or conventions proposed for this level of abstraction. Built-In Self-Test is a conventional DFT method, well defined in gate level and RT level. In this work by inspiration from the standard RTL BIST architectures, and finding similarities in TLM-2 designs and the RTL designs being tested by standard RTL BISTs, a number of TLM-2 BIST architectures are proposed. The overhead of inserting these BISTs in the original design is calculated.

Published in:

Test Symposium (ATS), 2011 20th Asian

Date of Conference:

20-23 Nov. 2011