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Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC

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4 Author(s)
Karimibiuki, M. ; Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada ; Balston, K. ; Hu, A.J. ; Ivanov, A.

Effective techniques for post-silicon validation are required to better evaluate functional correctness of increasingly complex SoCs. Coverage is the standard measure of validation effectiveness and is extensively used pre-silicon. However, there is little data evaluating the coverage of post-silicon validation efforts on industrial-scale designs. In this paper, we address this knowledge gap. We have developed an industrial-size SoC, based entirely on open-source IP: roughly a “netbook-on-a-chip”, synthesizable to FPGA, and capable of running Linux, X11, and application software. This platform allows us to instrument the hardware to measure true post-silicon coverage achieved by typical post-silicon validation tests, such as booting the OS - tests that are impossibly expensive to run in pre-silicon simulation. Thus, we can compare coverage achieved pre - and post-silicon, and also measure the area overhead required to monitor post-silicon coverage. In addition, we apply state-of-the-art software analysis techniques to reduce the instrumentation overhead for coverage monitoring. Our results show: (1) The typical test of booting the OS often achieves high coverage, well correlated to what is achieved by pre-silicon directed tests, but in some blocks the coverage can be markedly different, highlighting the importance of post-silicon validation in general and post-silicon coverage measurement in particular. (2) The area overhead of the coverage monitoring instrumentation is high, ranging from 1% to 22%. (3) State-of-the-art software analysis techniques reduce the overhead (e.g., nearly a 30% reduction for one block we instrumented), but the remaining overhead is still unacceptably high for practical deployment. Taken together, our results provide a solid baseline for further research on post-silicon coverage and test generation.

Published in:

High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International

Date of Conference:

9-11 Nov. 2011

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