By Topic

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Karputkin, A. ; Tallinn Univ. of Technol., Tallinn, Estonia ; Ubar, R. ; Tombak, M. ; Raik, J.

In this paper, a method is proposed that corrects RTL designs and builds on the sequential equivalence checking technique developed by the authors in [2], where the specification and the implementation are converted into High-Level Decision Diagrams (HLDD) [1]. In order to apply the proposed design error correction method, a certain degree of structural correspondence between the specification and the implementation at the level of circuit variables should be provided. Its application can be seen in engineering change applications where a part of an RTL implementation is altered.

Published in:

High Level Design Validation and Test Workshop (HLDVT), 2011 IEEE International

Date of Conference:

9-11 Nov. 2011