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Summary form only given. Scratchpad memories are largely used in embedded processorsdue to their reduced energy consumption and areacompared to traditional cache memories. In multi-core architectures, these memories are an interesting solution forthe storage of shared data and data which is used intensively.However, these memories present some challenges,such as the need for manual choice of the content. Furthermore,different sizes of scratchpad memories result inthe need to modify the source code of the application. Inthis article, we propose the use of a scratchpad memoryin a multi-core architecture which alleviates these disadvantages.We added the scratchpad to an architecture consistingof 4 cores, reducing the size of L2 cache in orderto give chip area to the scratchpad memory. We evaluatedour proposed design by executing the NAS Parallel Benchmark(NPB) applications in a simulator. We improved performanceby up to 45% compared to the base architecture,reducing cache invalidations by up to 85%.
Sistemas Computacionais (WSCAD-SSC), 2011 Simpasio em
Date of Conference: 26-29 Oct. 2011