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Evaluating the Problem of Process Mapping on Network-on-Chip for Parallel Applications

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4 Author(s)
Cintia P. Avelar ; Dept. of Comput. Sci., Pontifical Catholic Univ. of Minas, Belo Horizonte, Brazil ; Poliana A. C. Oliveira ; Henrique C. Freitas ; Philippe O. A. Navaux

Process mapping on Networks-on-Chip (NoC) is an important issue for the future many-core processors. Mapping strategies can increase performance and scalability by optimizing the communication cost. However, parallel applications have a large set of collective communication performing a high traffic on the Network-on-Chip. Therefore, our goal in this paper is to evaluate the problem related to the process mapping for parallel applications. The results show that for different mappings the performance is similar. The reason can be explained by collective communication due to the high number of packets exchanged by all routers. Our evaluation shows that topology and routing protocol can influence the process mapping. Consequently, for different NoC architectures different mapping strategies must be evaluated.

Published in:

Architecture and Multi-Core Applications (WAMCA), 2011 Second Workshop on

Date of Conference:

26-27 Oct. 2011