By Topic

A bit-level pipelined VLSI architecture for the running order algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chun-Te Chen ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Liang-Gee Chen ; Jue-Hsuan Hsiao

A bit-level pipelined VLSI architecture for the running order algorithm is presented. Based on the proposed modified algorithm, the deletion and the insertion is successfully pipelined in the bit-level operation. A block processing architecture of this modified algorithm is also constructed. The pipelined cycle of the proposed architecture is merely equivalent to the delay time of a pair of 1-bit comparisons that is independent on the window size and the signal resolution

Published in:

Signal Processing, IEEE Transactions on  (Volume:45 ,  Issue: 8 )