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An approach to code compression for CGRA

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2 Author(s)
Seongsik Park ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Kiyoung Choi

CGRA has been considered to be an attractive architecture for accelerating data-intensive applications due to the performance and flexibility that it can provide. However, the cache memory that stores the configuration code increases the silicon area significantly, making the architecture less attractive. This paper proposes an approach to saving the cache memory space through code compression for CGRA. It is based on the observation that typical configuration code consists of a repetition of same instruction patterns. Experiments with several applications show that the proposed approach reduces the code size by 56% on average and the required cache area by 26% on average and up to 68.6% when the hardware overhead is taken into account.

Published in:

Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on

Date of Conference:

19-20 July 2011

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