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Conventional six-transistor (6T) memory cell has an intrinsic data stability problem due to directly-accessed storage nodes during a read operation. The data stability issue becomes more severe with increasing variability and decreasing supply voltage in scaled CMOS technologies. Conventional techniques to enhance the data stability of 6T memory cells tend to sacrifice other important figures of merit, such as memory integration density and write ability. 6T SRAM circuits with higher data stability are presented in this paper. An electrical performance metric is evaluated to compare various memory design options targeting different applications. The overall electrical quality is enhanced without increasing the area with a multi-threshold-voltage CMOS technology. A high-threshold-voltage 6T memory cell is recommended for portable devices where lower energy consumption and longer battery lifetime are critically important. Alternatively, a triple-threshold-voltage 6T SRAM cell is recommended for robust memory operation in applications with aggressive speed requirement.