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NBTI-induced 8-Bit DAC circuit mismatch in System-On-Chip (SoC)

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3 Author(s)
Latif, M.A.A. ; Bayan Lepas FIZ, Intel Corp., Bayan Lepas, Malaysia ; Ali, N.B.Z. ; Hussin, F.A.

This paper focuses on Negative Bias Temperature Instability (NBTI) awareness to the circuit designer for reliable design of the System-On-a-Chip (SoC) analog circuit. The reliability performance of all matched pair such as current source and differential pair circuits, such as Bandgap Reference, is at the mercy of aging differential. Aging simulation (AgingSim) is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliability-critical device and NBTI is the most critical failure mechanism for analog circuit performance in sub-micrometer CMOS technology. This paper provides a complete reliability simulation analysis of an 8 bit Cathode-Ray-Tube (CRT) Digital-Analog-Converter (DAC) under 90nm process technology and analyze the effect of NBTI using aging simulation tool. A Burn-In experiment was performed to review the reliability sensitivity of the DAC design.

Published in:

Quality Electronic Design (ASQED), 2011 3rd Asia Symposium on

Date of Conference:

19-20 July 2011